1. Field of the Invention
The present invention is related to a wafer level package structure and the manufacturing method thereof, particularly related to a wafer level package structure for three dimensional stacking and the manufacturing method thereof.
2. Description of the Related Art
In order to meet the current requirements of portability and versatility on computer and consumer electronics products, the size hereof is required to be smaller and smaller while the integration density of integrated circuit chips becomes higher and higher. Due to the limitation of the available space, various packaging methods emerge, for example, the multi-chip module (MCM), flip chip package, three-dimensional (3D) stack package, and wafer level chip scale package (WLCSP). Basically, the concept of the wafer level packaging technology is that the chip scale packaging is executed on wafers. That is to say, during the wafer stage, most of the packaging work such as directly forming solder balls on an integrated circuit chip is completed, which not only omits the chip carrier such as a substrate or a lead frame in the conventional packaging technology, but also simplifies the packaging process. Therefore, the WLCSP can decrease the package size, and has considerable advantages regarding the process and the material costs.
In order to manufacture a semiconductor structure with higher integration density while not changing the form factor, it is inevitable that 3D packaging replaces two-dimensional (2D) packaging. Currently, the 3D stack package mostly uses a through-silicon-via (TSV) structure to achieve vertical electrical conduction, but the manufacturing costs and difficulty thereof are quite high. The present invention provides a special semiconductor package structure, in which repeated stacking is performed to achieve a 3D wafer level packaging.
In an improved wafer level package structure, fan-out wafer level package, a Redistribution Layer (RDL) extending out of a chip is formed on an active surface of the chip. The package structure only has a single surface capable of being arranged with solder balls to electrically connect to a printed circuit board; it thus cannot form a 3D die-to-die, 3D wafer-to-wafer, or 3D die-to-wafer stack structure.
Further, in the fan-out wafer level package, no carrier such as a substrate or a lead frame is used, and only an encapsulant is used to cover the chip, so that the structural strength thereof is insufficient. Moreover, the large difference in thermal expansion coefficient between the encapsulant and the chip is prone to induce warpage of the package which may further affect the reliability of the package structure.
In order to achieve a 3D stack wafer level package, the present invention provides a new structure and manufacturing method, so as to form the vertically conducted package structures at low cost and through a simplified process for further performing vertical stacking of semiconductor structures.